MSD integrated circuits with shallow trench

ABSTRACT

A trench MOSFET device with embedded Schottky rectifier, gate-drain and gate-source diodes on single chip is formed with shallow trench structure to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for GS clamp diodes and avalanche protection for GD clamp diodes. More particularly, gate charge of the present semiconductor device is reduced due to the shallow trench surrounded by an additional N doped area around the bottom while keeping Rds low enough and at the same time, maintaining BV at a certain level

FIELD OF THE INVENTION

This invention relates generally to the cell structure, deviceconfiguration and fabrication process of power semiconductor devices.More particularly, this invention relates to an improved cellconfiguration and processes to manufacture trench MOSFET device withSchottky rectifier, Gate-Drain (GD) and Gate-Source (GS) diodes withshallow trench structure on single chip for device shrinkage andperformance improvement.

BACKGROUND OF THE INVENTION

As shown in FIG. 1, normally for high efficiency DC/DC application, aSchottky rectifier is externally added in parallel with a MOSFET deviceto prevent a parasitic P/N body diode in the MOSFET from turning on inorder to achieve higher speed and efficiency. The requirement for theclamping effect is that the forward voltage of the Schottky rectifier Vfis less than the parasitic body PN diode (˜0.7V). Besides the Schottkyrectifier, a Gate-Source clamp diode with a breakdown voltage lower thanthe gate oxide rupture voltage of the MOSFET are provided for gate oxideESD (electrostatic discharge) protection. Moreover, a Gate-Drain clampdiode with a breakdown voltage lower than that of the MOSFET areprovided for Drain-Source avalanche protection. However, assembly ofthose separately structures into single package with extrainterconnection wires results in higher manufacturing cost, and poorperformance due to increase in inductance from the extra interconnectionwires.

Another constraint is that, when fabricating the structure shown in FIG.1, the conventional deep gate trenches are encountering a technicaldifficulty of high gate charge. The gate charge can be reduced simply bydecreasing trench depth and P-body depth. However, the decreases maylead to increase of Rds, and lower breakdown voltage in termination ifconventional field is used. As illustrated in FIG. 2, if the trench gateis not etched deep enough to a depth that the difference (Td-Pd) betweentrench depth Td and P-body depth Pd is less than 0.3 μm, Rds will besignificantly increased. In FIG. 2, there are two curves, the upper onerepresents no As I/I at the bottom of the trench, and the lower onerepresents there is an additional n-dopant doped area at the bottom oftrench which is our invention for resolving the Rds increasing issue dueto shallow trench, and the difference between the two curves will bediscussed below.

Accordingly, it would be desirable to provide more integrated trenchMOSFET device with embedded Schottky rectifier, Gate-Drain andGate-Source diodes on single chip for device shrinkage and performanceimprovement, and at the same time, having lower gate charge, lower Rdsand higher breakdown voltage.

SUMMARY OF THE INVENTION

It is therefore an aspect of the present invention to provide improvedsemiconductor power device configuration and manufacture processes forproviding trench MOSFET device with embedded Schottky rectifier,Gate-Drain and Gate-Source diodes with shallow trench structure onsingle chip so that space occupied can be reduced, and performanceimproved.

Another aspect of the present invention is to provide improvedsemiconductor power device configuration and manufacture processes forproviding trench MOSFET devices with embedded Schottky rectifier onsingle chip.

Another aspect of the present invention is to provide improvedsemiconductor power device configuration and manufacture processes forproviding trench MOSFET devices with embedded Schottky rectifier,Gate-Source diode on single chip.

Another aspect of the present invention is to provide improvedsemiconductor power device configuration and manufacture processes forproviding trench MOSFET devices with embedded Schottky rectifier,Gate-Drain diode on single chip.

Another aspect of the present invention is to provide improvedsemiconductor power device configuration and manufacture processes forproviding trench MOSFET devices with embedded Gate-Drain and Gate-Sourcediodes on single chip.

Another aspect of the present invention is to provide improvedsemiconductor power device configuration and manufacture processes forproviding trench MOSFET devices with embedded Schottky rectifier,Gate-Drain and Gate-Source diodes with shallow trench structure onsingle chip so that the gate charge can be reduced.

Another aspect of the present invention is that, in conventionalcondition, the using of shallow trench will lead to the increase of Rds,as Rds is dependent on the difference between trench depth and P-bodydepth, but in accordance with the present invention, this problem couldbe solved by forming an n dopant implantation area at the bottom of thetrench, as shown in FIGS. 2 and 3, the area 700 is implanted with As,and its concentration is heavier than it of epitaxial layer, asillustrated in FIG. 4, the dashed line indicates the concentration ofepitaxial layer, and it can be easily seen that the concentration of theN* area is heavier than that of the epitaxial layer. Refer to FIG. 2again, the lower curve means the Rds is reduced when using the N* areaat the bottom of the trench.

Another aspect of the present invention is that the bottom of the trenchis etched to be rounded instead of rectangular, by using of this method,the density of electrical field around the bottom of the trench is lowerthan the conventional structure, and the breakdown voltage is thusenhanced.

Briefly, in a preferred embodiment, the present invention discloses asemiconductor power device comprising a trench MOSFET with a trenchedjunction barrier Schottky rectifier and two diodes on single chip. Thetrenched junction barrier Schottky rectifier with a lower forwardvoltage is connected in parallel to the MOSFET as a clamp diode toprevent the parasitic PN body diode from turning on. The first Zenerdiode connects between a gate metal and a drain metal of saidsemiconductor power device functioning as a Gate-Drain clamp diode. TheGD clamp diode further includes multiple back-to-back doped regions in apolysilicon layer doped with dopant ions of a first conductivity typenext to a second conductivity type disposed on an insulation layer abovethe MOSFET device, having an avalanche voltage lower than a Source-Drainavalanche voltage of the MOSFET device wherein the Zener diode isinsulated from a doped region of the MOSFET device. The second Zenerdiode connects between a gate metal and a source metal of the saidMOSFET device for functioning as a Gate-Source clamp diode, wherein theGS clamp diode further includes multiple back-to-back doped regions in apolysilicon layer doped with dopant ions of a first conductivity typenext to a second conductivity type disposed on an insulation layer abovethe MOSFET device, having a lower breakdown voltage than a gate oxiderupture voltage of the MOSFET device. Underneath each trench bottom andtermination, an n* region doped with a concentration heavier than thatof epitaxial layer is formed to further reduce Rds. In an exemplaryembodiment, the structure disclosed is the same as the structurementioned in the first embodiment except that there is a trench Schottkydiode functioning as a clamp diode in parallel to the MOSFET device withthe parasitic PN body diode instead of the junction barrier Schottkyrectifier.

These and other objects and advantages of the present invention will nodoubt become obvious to those of ordinary skill in the art after havingread the following detailed description of the preferred embodiment,which is illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conventional application circuit of the MOSFET power devicewith integration of Schottky rectifier, GD and GS diodes in singlepackage.

FIG. 2 is a profile showing the dependence of Rds on difference betweentrench depth and P-body depth. The upper curve indicates the conditionwith no arsenic implantation at the bottom of the trench, while thelower one indicates the condition with an N* area at the bottom of thetrench.

FIG. 3 is a cross-section of a cell portion of a power MOS element ofthe present invention.

FIG. 4 is a profile illustrating the doping concentration distributedalong channel region from silicon surface.

FIG. 5A is a cross-section of an integrated trench MOSFET with embeddedjunction barrier Schottky rectifier, GD and GS diodes with shallowtrench structure of the first embodiment for the present invention. Thecross section location is identified with A-B line of Top View in FIG.5C

FIG. 5B is another cross-section of an integrated trench MOSFET withembedded junction barrier Schottky rectifier, GD and GS diodes withshallow trench structure of the first embodiment for the presentinvention. The cross section location is identified with C-D line of TopView in FIG. 5C

FIG. 5C is a top view of an integrated trench MOSFET with embeddedSchottky rectifier, GD and GS diodes with shallow trench structure ofthe first embodiment for the present invention.

FIG. 6 is a normalized measurement result of the relationship betweenbreakdown voltage and metal width cross over filed plate termination.

FIG. 7A is a cross-section of an integrated trench MOSFET with embeddedtrench Schottky rectifier, GD and GS diodes with shallow trenchstructure of another embodiment for the present invention. The crosssection location is identified with A-B line of Top View in FIG. 5C

FIG. 7B is another cross-section of an integrated trench MOSFET withembedded trench Schottky rectifier, GD and GS diodes with shallow trenchstructure of the second embodiment for the present invention. The crosssection location is identified with C-D line of Top View in FIG. 5C

FIGS. 8A to 8D are a serial of side cross sectional views showing theprocessing steps for fabricating a MOSFET device as shown in FIG. 7A andFIG. 7B of this invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Please refer to FIG. 5A to 5C for a first preferred embodiment of thisinvention. FIG. 5A is a cross-section A-B in FIG. 5C of this embodimentwhich shows a trenched MOSFET device 100 implemented with junctionbarrier Schottky rectifier 101, Gate-Source polysilicon Zener clampdiodes 102 and Gate-Drain polysilicon Zener clamp diodes 103 formed inan N epitaxial layer 200 above the a heavily N+ doped substrate 201coated with back metal of Ti/Ni/Ag 202 on rear side as drain. A trenchedgate 211 surrounded by a source region 212 encompassed in a body region213. An oxide layer 204 covering the trenched semiconductor power devicewith a source-body contact trench 215 opened through and extending intothe source and body regions and filled with tungsten plugs therein. Alayer of Al Alloys or Copper 203 over Ti or Ti/TiN layer (not shown)serves as source metal on an oxide layer 204 deposited along the topsurface of the insulation layer 214. The region 216 is heavily P dopedto reduce the resistance between said trench contact metal plug 215 andsaid body region. The junction barrier Schottky contact trench 217 isformed in said N epitaxial layer with other contact trench 218 formed inthe P-well 219 adjacent to said junction barrier Schottky contact trenchfilled with Tungsten plug connected to said source metal serving asanode of said Schottky rectifier. In order to provide the Gate-Sourcepolysilicon Zener clamp diodes 102 and Gate-Drain polysilicon Zenerclamp diodes 103, a polysilicon layer are formed on said oxide layer 204and doped as alternating N+ and P+ regions adjacent to each other. TheN+ doped polysilicon regions 102N1, 102N2 and the P+ doped polysiliconregion 102P constitute the GS polysilicon Zener clamp diodes 102 whilethe N+ doped regions 103N1, 103N2 and the P+ doped polysilicon region103P constitute the GD polysilicon Zener clamp diodes 103. The contacttrench 220 is formed to connect the source metal with the N+dopedpolysilicon region 102N1 of the GS polysilicon Zener clamp diodes. Thecontact trench 221 is formed to connect the gate metal with the N+ dopedpolysilicon region 102N2 of the GS polysilicon Zener clamp diodes. Thecontact trench 222 is formed to connect the gate metal with the N+ dopedpolysilicon region 103N1 of the GD polysilicon Zener clamp diodes. Andthe contact trench 223 is formed to connect the drain metal with the N+doped polysilicon region 103N2 of the GD polysilicon Zener clamp diodes.Trench gates 205 are formed underneath the contact trench 220, 221 222and 223 acting as a buffer layer to avoid the zener diodes shorting withthe P-body 213. It should be noticed that, the bottom of each trench, asshown in FIG. 5A, is designed to be rounded to form shallow trench forfurther reducing gate charge. Underneath each trench bottom andtermination, an N* region 700 is formed by arsenic Ion Implantation tofurther reduce Rds caused by decreasing the trench depth.

FIG. 5B is another cross-section C-D of the first embodiment as shown inFIG. 5C. The only difference between FIG. 5B and FIG. 5A is that thereis an open area 250 of the drain metal on the top of the termination. Aconventional metal field plate in the termination is provided to sustainbreakdown voltage.

FIG. 5C is a top view of the first embodiment which shows Gate-Draindiode across termination with the open areas 250 in FIG. 5B of the drainmetal. These open areas allow electrical field penetrate through theoxides during avalanche, and thus make benefits to avoid avalanchedegradation caused by the metal field plate cross over the terminationas shown in FIG. 5A.

FIG. 6 is a normalized measurement result of the relationship betweenbreakdown voltage and metal width cross over metal field platetermination, which shows that breakdown voltage will be degraded whenmetal width W is greater than 5 um, It means that electrical fieldunderneath the cross-over metal can not effectively goes through theopen area 250 if the metal width is larger than 5 um.

FIG. 7A is the cross-section A-B of the second embodiment of the presentinvention. The only difference between the structure of FIG. 7A and FIG.5.A is that the embedded Schottky rectifier is a trench Schottkyrectifier instead of junction barrier Schottky rectifier. The trenchSchottky contact trench 272 is formed in said N epitaxial layer andother contact trench 271 formed in the trench gate 270 adjacent to saidcontact trench.

FIG. 7B is another cross-section C-D of the second embodiment. The onlydifference between FIG. 7B and FIG. 7A is that there is an open area 251of the drain metal on the top of the termination.

FIGS. 8A to 8D is a serial of exemplary steps that are performed to formthe inventive device configuration of FIG. 7A. FIG. 8A shows that an Ndoped epitaxial layer 200 is grown on an N+ doped substrate 201. Atrench mask (not shown) is applied to open a plurality of trenches byemploying a dry silicon etch process. In order to remove the plasmadamage introduced in etching said trenches, a sacrificial oxide layer isoxidized and then removed. A layer of screen oxide is grown for anArsenic Ion Implantation process to form the N* region 700, and thenremoved to continue with the gate oxidation. After the formation of thegate oxide, doped poly is filled into the trenches and then etched back,serving as the gate material. A P-body mask is employed in the P-bodyIon Implantation and followed by diffusion process to give a certaindepth to form the body region 213, and an oxide layer 214 is grown onthe top of the entire structure.

In FIG. 8B, a layer of undoped poly is deposited on the surface of thestructure, and a poly mask is applied in a dry silicon etch process toform GS polysilicon Zener clamp diodes 102 and GD polysilicon Zenerclamp diodes 103 after a Blank Boron Ion Implantation. Next, an N+source mask is employed in the N+ source Ion Implantation and followedby diffusion process to give a certain depth to form the cathodes ofsaid Zener clamp diodes, source region 212 and N+ region 240.

In FIG. 8C, an oxide layer is deposited to cover the entire structure,and a contact mask is employed in a dry silicon etch process. After theformation of all the contact trenches, a BF2 mask is employed in the BF2Ion Implantation to form the more heavily doped region 216 to reduce theresistance between said trench contact metal plug and said body region.

In FIG. 8D, a layer of Ti/TiN, Co/TiN or Mo/TiN (not shown) is depositedalong the sidewall of each trench. To fill the contact trenches,tungsten is deposited serving as plug metal followed by a CMP process.Last, a metal mask is employed in the deposition process to form a layerof front metal of Al Alloys 203 above the entire structure.

Although the present invention has been described in terms of thepresently preferred embodiments, it is to be understood that suchdisclosure is not to be interpreted as limiting. Various alternationsand modifications will no doubt become apparent to those skilled in theart after reading the above disclosure. Accordingly, it is intended thatthe appended claims be interpreted as covering all alternations andmodifications as fall within the true spirit and scope of the invention.

1. An integrated circuit compromises trench MOSFET, Schottky rectifier,Gate-Drain and Gate-Source clamp diodes with shallow trench contactstructure for device shrinkage and performance improvement on singlechip wherein: a substrate of the first conductivity type; an epitaxiallayer of said first conductivity type over said substrate, saidepitaxial layer having a lower doping than said substrate; a trenchMOSFET comprising a trenched gate surrounded by a source region of saidfirst conductivity type encompassed in a body region of secondconductivity type above a drain region disposed on a bottom surface of asubstrate; a gate oxide lining said trenches; a doped polysilicon withinsaid trenches and overlying said gate oxide; a Schottky rectifierextending into said epitaxial layer and having a Schottky barrier layerlined in trench contacts filled with Schottky barrier layer and contactmetal plug; an insulation layer covering said integrity circuit with asource-body contact trench opened through and extending into said sourceand body regions in trench MOSFET and filled with metal plugs therein; alayer of Al Alloys or Copper serves as source metal on an oxide layerdeposited along the top surface of said insulation layer and said metalplug; a heavily doped region of the second conductivity type formedaround said contact trench bottom to reduce the resistance between saidtrench contact metal plug and said body regions; a Gate-Drain clampdiode compromises a plurality of back to back polysilicon zener diodewith dopant ions of a first conductivity type next to a secondconductivity type, connected with gate on one side, and drain on anotherside through a plurality metal stripe cross over termination area; aGate-Source Clamp diode compromises a plurality of back to backpolysilicon zener diode with dopant ions of a first conductivity typenext to a second conductivity type, connected with gate on one side, andsource on another side; a region have heavier doping concentration thansaid epitaxial layer with same type doping underneath each said trenchbottom and in top surface of termination in said integrated circuit; andat least a gate contact trench opened through said insulation layercovering said semiconductor power device wherein said gate contacttrench penetrating from said insulation layer and extending into atrench-filling material in said trenched gate underneath gate runnermetal.
 2. The integrated circuits of claim 1 wherein: said the Schottkyrectifier is trench Schottky rectifier having a Schottky barrier layerof Ti/TiN, Co/TiN or Mo/TiN lined in trench contact filled with contactmetal plug and between a pair of adjacent trenches.
 3. The integratedcircuits of claim 1 wherein: said the Schottky rectifier is JunctionBarrier Schottky rectifier having a Schottky barrier layer of Ti/TiN,Co/TiN or Mo/TiN lined in trench contact filled with contact metal plugand between a pair of adjacent P wells.
 4. The integrated circuits ofclaim 1 wherein: said the contact metal plug is tungsten (W) overlyingsaid barrier layer of Ti/TiN, Co/TiN or Mo/TiN, and connected to Alalloys or Copper source metal through a Ti or Ti/TiN layer for reductionof contact resistance between W and source metals.
 5. The integratedcircuits of claim 1 wherein: said the contact metal plug is said thesource metal Al alloys or Copper overlying said barrier layer of Ti/TiN,Co/TiN or Mo/TiN.
 6. The Integrated circuits device of claim 1 wherein:said integrated circuit comprising a N-channel trench MOSFET, and saidGate-Drain and Gate-Source Clamp diodes comprising multiple back-to-backdoped regions in said polysilicon layer doped with N+ dopant ions nextto a P dopant ions.
 7. The Integrated circuits device of claim 1wherein: said trench gates underneath contact areas of said Gate-Drainand Gate-source Clamp diodes act as buffer layer for prevention ofshortage between said the diodes and body regions.
 8. An integratedcircuit compromises trench MOSFET, Schottky rectifier and Gate-Sourceclamp diodes with shallow trench contact structure for device shrinkageand performance improvement on single chip wherein: a substrate of thefirst conductivity type; an epitaxial layer of said first conductivitytype over said substrate, said epitaxial layer having a lower dopingthan said substrate; a trench MOSFET comprising a trenched gatesurrounded by a source region of said first conductivity typeencompassed in a body region of second conductivity type above a drainregion disposed on a bottom surface of a substrate; a gate oxide liningsaid trenches; a doped polysilicon within said trenches and overlyingsaid gate oxide; a Schottky rectifier extending into said epitaxiallayer and having a Schottky barrier layer lined in trench contactsfilled with Schottky barrier layer and contact metal plug; an insulationlayer covering said integrity circuit with a source-body contact trenchopened through and extending into said source and body regions in trenchMOSFET and filled with metal plugs therein. a layer of Al Alloys orCopper serves as source metal on an oxide layer deposited along the topsurface of said insulation layer and said metal plug. a heavily dopedregion of the second conductivity type formed around said contact trenchbottom to reduce the resistance between said trench contact metal plugand said body regions. a Gate-Source Clamp diode compromises a pluralityof back to back polysilicon zener diode with dopant ions of a firstconductivity type next to a second conductivity type, connected withgate on one side, and source on another side. a region have heavierdoping concentration than said epitaxial layer with same type dopingunderneath each said trench bottom and termination in the power devicesin top surface of termination in said integrated circuit; and at least agate contact trench opened through said insulation layer covering saidsemiconductor power device wherein said gate contact trench penetratingfrom said insulation layer and extending into a trench-filling materialin said trenched gate underneath gate runner metal.
 9. The integratedcircuits of claim 8 wherein: said the Schottky rectifier is trenchSchottky rectifier having a Schottky barrier layer of Ti/TiN, Co/TiN orMo/TiN lined in trench contact filled with contact metal plug andbetween a pair of adjacent trenches.
 10. The integrated circuits ofclaim 8 wherein: said the Schottky rectifier is Junction BarrierSchottky rectifier having a Schottky barrier layer of Ti/TiN, Co/TiN orMo/TiN lined in trench contact filled with contact metal plug andbetween a pair of adjacent P wells.
 11. The integrated circuits of claim8 wherein: said the contact metal plug is tungsten (W) overlying saidbarrier layer of Ti/TiN, Co/TiN or Mo/TiN, and connected to Al alloys orCopper source metal through a Ti or Ti/TiN layer for reduction ofcontact resistance between W and source metals.
 12. The integratedcircuits of claim 8 wherein: said the contact metal plug is said thesource metal Al alloys or Copper overlying said barrier layer of Ti/TiN,Co/TiN or Mo/TiN.
 13. The Integrated circuits device of claim 8 wherein:said trench gates underneath contact areas of said Gate-source Clampdiode act as buffer layer for prevention of shortage between said thediodes and body regions.
 14. The Integrated circuits device of claim 8wherein: said integrated circuit comprising a N-channel trench MOSFET,and said Gate-Source Clamp diodes comprising multiple back-to-back dopedregions in said polysilicon layer doped with N+ dopant ions next to a Pdopant ions.
 15. An integrated circuit compromises trench MOSFET,Schottky rectifier and Gate-Drain clamp diode with shallow trenchcontact structure for device shrinkage and performance improvement onsingle chip wherein: a substrate of the first conductivity type; anepitaxial layer of said first conductivity type over said substrate,said epitaxial layer having a lower doping than said substrate; a trenchMOSFET comprising a trenched gate surrounded by a source region of saidfirst conductivity type encompassed in a body region of secondconductivity type above a drain region disposed on a bottom surface of asubstrate; a gate oxide lining said trenches; a doped polysilicon withinsaid trenches and overlying said gate oxide; a Schottky rectifierextending into said epitaxial layer and having a Schottky barrier layerlined in trench contacts filled with Schottky barrier layer and contactmetal plug; an insulation layer covering said integrity circuit with asource-body contact trench opened through and extending into said sourceand body regions in trench MOSFET and filled with metal plugs therein; alayer of Al Alloys or Copper serves as source metal on an oxide layerdeposited along the top surface of said insulation layer and said metalplug; a heavily doped region of the second conductivity type formedaround said contact trench bottom to reduce the resistance between saidtrench contact metal plug and said body regions; a Gate-Drain clampdiode compromises a plurality of back to back polysilicon zener diodewith dopant ions of a first conductivity type next to a secondconductivity type, connected with gate on one side, and drain on anotherside through a plurality metal stripe cross over termination area; aregion have heavier doping concentration than said epitaxial layer withsame type doping underneath each said trench bottom and in top surfaceof termination in said integrated circuit; and at least a gate contacttrench opened through said insulation layer covering said semiconductorpower device wherein said gate contact trench penetrating from saidinsulation layer and extending into a trench-filling material in saidtrenched gate underneath gate runner metal.
 16. The integrated circuitsof claim 15 wherein: said the Schottky rectifier is trench Schottkyrectifier having a Schottky barrier layer of Ti/TiN, Co/TiN or Mo/TiNlined in trench contact filled with contact metal plug and between apair of adjacent trenches.
 17. The integrated circuits of claim 15wherein: said the Schottky rectifier is Junction Barrier Schottkyrectifier having a Schottky barrier layer of Ti/TiN, Co/TiN or Mo/TiNlined in trench contact filled with contact metal plug and between apair of adjacent P wells.
 18. The integrated circuits of claim 15wherein: said the contact metal plug is tungsten (W) overlying saidbarrier layer of Ti/TiN, Co/TiN or Mo/TiN, and connected to Al alloys orCopper source metal through a Ti or Ti/TiN layer for reduction ofcontact resistance between W and source metals.
 19. The integratedcircuits of claim 15 wherein: said the contact metal plug is said thesource metal Al alloys or Copper overlying said barrier layer of Ti/TiN,Co/TiN or Mo/TiN.
 20. The Integrated circuits device of claim 15wherein: said trench gates underneath contact areas of said Gate-sourceClamp diode act as buffer layer for prevention of shortage between saidthe diodes and body regions.
 21. The Integrated circuits device of claim15 wherein: said integrated circuit comprising a N-channel trenchMOSFET, and said Gate-Drain Clamp diode comprising multiple back-to-backdoped regions in said polysilicon layer doped with N+ dopant ions nextto a P dopant ions. The trench gates are underneath contact areas ofsaid Gate-Drain diode.
 22. An integrated circuit compromises trenchMOSFET, Gate-Drain and Gate-Source clamp diodes with shallow trenchcontact structure for device shrinkage and performance improvement onsingle chip wherein: a substrate of the first conductivity type; anepitaxial layer of said first conductivity type over said substrate,said epitaxial layer having a lower doping than said substrate; a trenchMOSFET comprising a trenched gate surrounded by a source region of saidfirst conductivity type encompassed in a body region of secondconductivity type above a drain region disposed on a bottom surface of asubstrate; a gate oxide lining said trenches; a doped polysilicon withinsaid trenches and overlying said gate oxide; an insulation layercovering said integrity circuit with a source-body contact trench openedthrough and extending into said source and body regions in trench MOSFETand filled with metal plugs therein; a layer of Al Alloys or Copperserves as source metal on an oxide layer deposited along the top surfaceof said insulation layer and said metal plug; a heavily doped region ofthe second conductivity type formed around said contact trench bottom toreduce the resistance between said trench contact metal plug and saidbody regions; a Gate-Drain clamp diode compromises a plurality of backto back polysilicon zener diode with dopant ions of a first conductivitytype next to a second conductivity type, connected with gate on oneside, and drain on another side through a plurality metal stripe crossover termination area; a Gate-Source Clamp diode compromises a pluralityof back to back polysilicon zener diode with dopant ions of a firstconductivity type next to a second conductivity type, connected withgate on one side, and source on another side; a region have heavierdoping concentration than said epitaxial layer with same type dopingunderneath each said trench bottom and in top surface of termination insaid integrated circuit; and at least a gate contact trench openedthrough said insulation layer covering said semiconductor power devicewherein said gate contact trench penetrating from said insulation layerand extending into a trench-filling material in said trenched gateunderneath gate runner metal.
 23. The integrated circuits of claim 22wherein: said the contact metal plug is tungsten (W) overlying saidbarrier layer of Ti/TiN, Co/TiN or Mo/TiN, and connected to Al alloys orCopper source metal through a Ti or Ti/TiN layer for reduction ofcontact resistance between W and source metals.
 24. The integratedcircuits of claim 22 wherein: said the contact metal plug is said thesource metal Al alloys or Copper overlying said barrier layer of Ti/TiN,Co/TiN or Mo/TiN.
 25. The Integrated circuits device of claim 22wherein: said integrated circuit comprising a N-channel trench MOSFET,and said Gate-Drain and Gate-Source Clamp diodes comprising multipleback-to-back doped regions in said polysilicon layer doped with N+dopant ions next to a P dopant ions.
 26. The Integrated circuits deviceof claim 22 wherein: said trench gates underneath contact areas of saidGate-source and Gate-Drain Clamp diodes act as buffer layer forprevention of shortage between said the diodes and body regions.
 27. Anintegrated circuit compromises trench MOSFET and Gate-Source clamp diodewith shallow trench contact structure for device shrinkage andperformance improvement on single chip wherein: a substrate of the firstconductivity type; an epitaxial layer of said first conductivity typeover said substrate, said epitaxial layer having a lower doping thansaid substrate; a trench MOSFET comprising a trenched gate surrounded bya source region of said first conductivity type encompassed in a bodyregion of second conductivity type above a drain region disposed on abottom surface of a substrate; a gate oxide lining said trenches; adoped polysilicon within said trenches and overlying said gate oxide; aninsulation layer covering said integrity circuit with a source-bodycontact trench opened through and extending into said source and bodyregions in trench MOSFET and filled with metal plugs therein; a layer ofAl Alloys or Copper serves as source metal on an oxide layer depositedalong the top surface of said insulation layer and said metal plug; aheavily doped region of the second conductivity type formed around saidcontact trench bottom to reduce the resistance between said trenchcontact metal plug and said body regions. a Gate-Source Clamp diodecompromises a plurality of back to back polysilicon zener diode withdopant ions of a first conductivity type next to a second conductivitytype, connected with gate on one side, and source on another side; aregion have heavier doping concentration than said epitaxial layer withsame type doping underneath each said trench bottom and in top surfaceof termination in said integrity circuit; and at least a gate contacttrench opened through said insulation layer covering said semiconductorpower device wherein said gate contact trench penetrating from saidinsulation layer and extending into a trench-filling material in saidtrenched gate underneath gate runner metal.
 28. The Integrated circuitsdevice of claim 27 wherein: said integrated circuit comprising aN-channel trench MOSFET, and said Gate-Source Clamp diodes comprisingmultiple back-to-back doped regions in said polysilicon layer doped withN+ dopant ions next to a P dopant ions.
 29. The integrated circuits ofclaim 27 wherein: said the contact metal plug is tungsten (W) overlyingsaid barrier layer of Ti/TiN, Co/TiN or Mo/TiN, and connected to Alalloys or Copper source metal through a Ti or Ti/TiN layer for reductionof contact resistance between W and source metals.
 30. The integratedcircuits of claim 27 wherein: said the contact metal plug is said thesource metal Al alloys or Copper overlying said barrier layer of Ti/TiN,Co/TiN or Mo/TiN.
 31. The Integrated circuits device of claim 27wherein: said trench gates underneath contact areas of said Gate-sourcediode act as buffer layer for prevention of shortage between said thediodes and body regions.
 32. An integrated circuit compromises trenchMOSFET and Gate-Drain clamp diode with shallow trench contact structurefor device shrinkage and performance improvement on single chip wherein:a substrate of the first conductivity type; an epitaxial layer of saidfirst conductivity type over said substrate, said epitaxial layer havinga lower doping than said substrate; a trench MOSFET comprising atrenched gate surrounded by a source region of said first conductivitytype encompassed in a body region of second conductivity type above adrain region disposed on a bottom surface of a substrate; a gate oxidelining said trenches; a doped polysilicon within said trenches andoverlying said gate oxide; an insulation layer covering said integritycircuit with a source-body contact trench opened through and extendinginto said source and body regions in trench MOSFET and filled with metalplugs therein; a layer of Al Alloys or Copper serves as source metal onan oxide layer deposited along the top surface of said insulation layerand said metal plug; a heavily doped region of the second conductivitytype formed around said contact trench bottom to reduce the resistancebetween said trench contact metal plug and said body regions; aGate-Drain clamp diode compromises a plurality of back to backpolysilicon zener diode with dopant ions of a first conductivity typenext to a second conductivity type, connected with gate on one side, anddrain on another side through a plurality metal stripe cross overtermination area; a region have heavier doping concentration than saidepitaxial layer with same type doping underneath each said trench bottomand in top surface of termination in said integrity circuit; and atleast a gate contact trench opened through said insulation layercovering said semiconductor power device wherein said gate contacttrench penetrating from said insulation layer and extending into atrench-filling material in said trenched gate underneath gate runnermetal.
 33. The integrated circuits of claim 32 wherein: said the contactmetal plug is tungsten (W) overlying said barrier layer of Ti/TiN,Co/TiN or Mo/TiN, and connected to Al alloys or Copper source metalthrough a Ti or Ti/TiN layer for reduction of contact resistance betweenW and source metals.
 34. The integrated circuits of claim 32 wherein:said the contact metal plug is said the source metal Al alloys or Copperoverlying said barrier layer of Ti/TiN, Co/TiN or Mo/TiN.
 35. TheIntegrated circuits device of claim 32 wherein: said trench gatesunderneath contact areas of said Gate-Drain Clamp diode act as bufferlayer for prevention of shortage between said the diodes and bodyregions.
 36. The Integrated circuits device of claim 32 wherein: saidintegrated circuit comprising a N-channel trench MOSFET, and saidGate-Drain Clamp diodes comprising multiple back-to-back doped regionsin said polysilicon layer doped with N+ dopant ions next to a P dopantions.